Design-Reuse

Xilinx Ultra-Small CPLD Packaging Enables High Performance Sketchpad DSP Boards for 3DSP

SAN JOSE, Calif., January 29, 2003 - Xilinx, Inc., (NASDAQ:XLNX) today announced that 3DSP, a leading provider of configurable, scalable digital signal processor (DSP) architecture, used Xilinx chip ...
EDN

Xilinx axes analog to cool CPLD power consumption

SAN MATEO, Calif. — Are complex programmable-logic devices (CPLDs) in their current form about to reach the end of the road? Xilinx Inc. believes that they are, and says the only way to keep scaling ...
EDN

New Tool Consolidates CPLD Logic Design

Xilinx, Inc. the world's leading programmable logic supplier, announced availability of the CPLD Logic Consolidator. This analysis tool permits digital designers and production managers to compare ...
Design-Reuse

Xilinx Announces ISE WebPACK 9.1i Release - Delivering Highest System Performance and Fastest Compile Time

Free downloadable design suite for both Windows and Linux delivers on average 10% lower dynamic power, and expanded FPGA device support January 22, 2007, SAN JOSE, Calif. – Xilinx, Inc. (NASDAQ: ...
Hackaday

CPLD-Based Synchronization Of Multiple Software Defined Radios

Forgive the click bait headline, but the latest work from [Marco Bartolucci] and [José A. del Peral-Rosado] is really great. They’re using multiple HackRFs, synchronized together, with hybrid ...