EDN

Specify an external reference clock to improve SERDES performance

The technical merits and economic benefits of high-speed serial data transmission on a circuit board or between neighboring circuit boards have led to the development of many high-speed serial ...
EDN

Evaluate reference clocks for serial-data jitter specifications

Almost all high-speed SERDES designs require reference clocks that you must properly select to ensure that your links meet jitter requirements of high-speed serial-data communication standards.
Electronic Design

Optimal Jitter Attenuation Starts With The Proper PLL Bandwidth

Clock signals provide reference timing to every integrated circuit and electrical system. Consumer applications typically use simple quartz crystals for reference clock generation. Other applications, ...
Design-Reuse

Lattice Semiconductor and Epson Toyocom Provide Low-Cost, High Frequency Differential Reference Clock Solution

HILLSBORO, OR -- Oct 12, 2009-- Lattice Semiconductor (NASDAQ: LSCC) and Epson Toyocom Corporation today announced a low-cost reference clock solution for SERDES applications. By utilizing Lattice's ...
Electronic Design

Design A Clock-Distribution Strategy With Confidence

Clock-distribution devices create multiple copies of a master clock and distribute them to a variety of integrated circuits. They accept single-ended or differential clock inputs and supply multiple ...