The purpose of this application note is to familiarize the reader with the Level 1 (L1) CPU cache implementation in the PIC32MZ device family by bringing awareness to the hazards that can occur in a ...

Open Core Protocol (OCP) [1][2] is a common standard for Intellectual Property (IP)core interfaces. OCP facilitates IP core plug-and-play and simplifies reuse by decoupling the cores from the on-chip ...

A processor cache is an area of high-speed memory that stores information near the processor. This helps make the processing of common instructions efficient and therefore speeds up computation time.

As discussed in part one, one of the reasons cache coherency is becoming more important is the shared common memory resource in designs today. Various agents in the design want to access the data the ...