Design-Reuse

Lattice Announces Immediate Availability of DDR SDRAM Controller IP Core for LatticeECP and LatticeEC FPGA Families

Pipelined Intellectual Property Core Validated In-System At 200MHz/400DDR; Designed For High-Speed Operation Using Embedded DDR Support In LatticeECP/LatticeEC FPGA Devices The Double Data Rate (DDR) ...
EDN

Lattice Delivers Flexible, Programmable 40 Gbps Serdes Framer Interface, Level 5 (SFI5) IP Core Solution

Lattice announced the availability of the 40 Gbps SERDES Framer Interface, Level 5 (SFI5) Intellectual Property (IP) Core in the LatticeSC and LatticeSCM FPGA families. Lattice announced the ...
Design-Reuse

Lattice and Oregano Systems Announce Comprehensive Versions of the IEEE-1588 Timing Node System IP Core

HILLSBORO, OR-- May 3, 2011 - Lattice Semiconductor Corporation (NASDAQ:LSCC - News) and Oregano Systems - Design & Consulting Ltd. today announced the immediate availability of three comprehensive ...
Nasdaq

Lattice and SiFive Announce Collaboration to Allow Lattice FPGA Developers Easy Access to RISC-V Processors

Scalable Processor Core IP Running on Low Power, Small Form Factor FPGAs Could Power Millions of Smart Devices at the Edge The need for intelligent processing at the Edge and endpoint is increasing, ...
Nasdaq

Lattice Accelerates FPGA-Based Processor Design With New IP Ecosystem and Design Environment

Lattice Propel Provides RISC-V Support and a Robust IP Portfolio to Enable Development of Processor-based Systems in Minutes HILLSBORO, Ore.--(BUSINESS WIRE)-- Lattice Semiconductor Corporation ...
Electronic Design

Lattice Launches IP Ecosystem and Design Environment to Accelerate Processor-based Development

Lattice Semiconductor launched Lattice Propel, a software solution designed to accelerate development of novel applications based on low-power, small form-factor Lattice FPGAs. The design environment ...
Business Wire

InterMotion Technology Boosts IP Verification Productivity for Lattice Semiconductor’s CrossLink FPGA Family Using Aldec’s Active-HDL

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, today announced that InterMotion Technology has ...