Design-Reuse

Extending RISC-V ISA With a Custom Instruction Set Extension

RISC-V ISA (Instruction Set Architecture) is designed in a modular way. It means that the ISA has several groups of instructions (ISA extensions) that can be enabled or disabled as needed. This allows ...
Hackaday

Checking In On The ISA Wars And Its Impact On CPU Architectures

An Instruction Set Architecture (ISA) defines the software interface through which for example a central processor unit (CPU) is controlled. Unlike early computer systems which didn’t define a ...
New Electronics

Codasip Whitepaper - Creating domain-specific processors using custom RISC-V ISA instructions

When System-on-Chip (SoC) developers include processors in their designs, they face choices in solving their computational challenges, as Codasip CTO Zdeněk Přikryl explains in this whitepaper.
Ars Technica

AMD announces 128-bit (GPU-oriented?) SSE5 extensions to x86

AMD is looking to repeat the market-leading success they had with x86-64 by introducing another major change to the venerable x86 ISA: a three-operand instruction format for vector instructions in the ...
Design-Reuse

Creating Domain Specific Processors Using Custom RISC-V ISA Instructions

When System-on-Chip (SoC) developers include processors in their designs, they face choices in solving their computational challenges. Complex SoCs will usually have a variety of processor cores ...