EDN

Transistor level ESD verification in large SoC designs

When it comes to large system-on-chip (SoC) designs, there is a need for a comprehensive electrostatic discharge (ESD) verification flow that can verify both topological and geometrical constructions ...
Business Wire

Apache Introduces PathFinder, the Industry’s First Full-chip ESD Physical Integrity Solution

SAN JOSE, Calif.--(BUSINESS WIRE)--Apache Design Solutions, the technology leader in power integrity and noise closure for chip-package-systems (CPS) convergence, today announced PathFinder™, a ...
EDN

Vertical BJT Type ESD Device

MagnaChip Semiconductor Corporation, a Korea-based designer and manufacturer of analog and mixed signal semiconductor products, announced that it now offers a vertical BJT (Bipolar Junction Transistor ...
Semiconductor Engineering

No More Netlist Hacking

Prior to availability of advanced physical verification tools, it was not uncommon for engineering teams to hack netlists. It sounds very clandestine, but was done out of the need to get detailed ...
Semiconductor Engineering

Verifying Your Intent

Design rule checking (DRC), layout versus schematic (LVS) and electrical rule checking (ERC) are physical verification techniques that are mandatory today to check a design and its structures before ...